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D a t a S he et , V 1. 1, J u l y 2 00 3
HYS[64/72]D64x20GU-x-B HYS[64/72]D32x00[G/E]U-x-B HYS64D16301GU-x-B
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es U D IM M DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2003-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S he et , V 1. 1, J u l y 2 00 3
HYS[64/72]D64x20GU-x-B HYS[64/72]D32x00[G/E]U-x-B HYS64D16301GU-x-B
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es U D IM M DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, HYS64D16301GU-x-B Revision History: Previous Version: Page all all 10 19ff 20ff 24f 26f 29ff 41ff 8 9 44ff V1.1 V1.01 2003-07 2003-01
Subjects (major changes since last revision) new data sheet template replace bank by rank if DIMM related (4 bank SDRAM on 1 or 2 rank DIMM) Table 6: Address Table updated Table 10ff: IDD conditions now in seperate table Table 11ff: added part numbers to IDD tables Table 15: split in two tables (now 15 & 16) Table 16: add -5 (DDR400) Chapter 4: added part numbers to SPD tables Table 21: set Bytes 47-55 to not used (00hex); set byte 62 to SPD rev. 0.0 (00hex); update Checksum (TPCR) Table 4: Changed RAS/CAS/WE description to command inputs and amended CLK to CK Table 5: Changed CLK to CK Figure 7 - Figure 13 Amended and updated package outline drawings
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 19 24
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Sheet
5
V1.1, 2003-07
184-Pin Unbuffered Dual-In-Line Memory Modules UDIMM
HYS[64/72]D64x20GU-x-B HYS[64/72]D32x00[G/E]U-x-B HYS64D16301GU-x-B
1
1.1
* * * * * * * * * * * * *
Overview
Features
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory applications One rank 16M x 64, 32M x 64, 32M x 72 and two ranks 64M x 64, 64M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (0.2V) power supply Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM JEDEC standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. Jedec standard reference layout Gold plated contacts DDR400 Speed Grade supported Lead- & halogene-free DIMM available Performance -5 DDR400B PC3200 -3033 200 166 133 -6 DDR333B PC2700 -2533 166 166 133 -7F DDR266 PC2100 -2022 - 143 133 -7 DDR266A PC2100 -2033 - 143 133 -8 DDR200 PC1600 -2022 - 125 100 Unit - - MHz MHz MHz
Table 1
Part Number Speed Code Module Speed Grade Component Module max. Clock Frequency
fCK3 @ CL = 2.5 fCK2.5 @ CL = 2 fCK2
@ CL = 3
1.2
Description
The HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, and HYS64D16301GU-x-B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules (UDIMM) organized as 32M x 64 and 64M x 64 for non-parity and 32M x 72 and 64M x 72 for ECC main memory applications. The memory array is designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer
Data Sheet
6
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Overview Table 2 Type PC3200 (CL=3) HYS64D16301GU-5-B HYS64D32300GU-5-B HYS72D32300GU-5-B HYS64D64320GU-5-B HYS72D64320GU-5-B PC2700 (CL=2.5) HYS64D16301GU-6-B HYS64D32300GU-6-B HYS72D32300GU-6-B HYS64D64320GU-6-B HYS72D64320GU-6-B PC2100 (CL=2) HYS64D16301GU-7-B HYS64D32000GU-7-B HYS72D32000GU-7F-B HYS72D32000GU-7-B HYS64D64020GU-7-B HYS72D64020GU-7F-B HYS72D64020GU-7-B PC1600 (CL=2) HYS64D16301GU-8-B HYS64D32000GU-8-B HYS72D32000GU-8-B HYS64D64020GU-8-B HYS72D64020GU-8-B Table 3 Type PC2100 (CL=2) HYS64D32300EU-7-B PC2100U-20330-A1 one rank 256MB DIMM 256 Mbit (x 8) PC1600U-20330-C2 PC1600U-20220-A1 PC1600U-20220-A1 PC1600U-20220-B1 PC1600U-20220-B1 one rank 128MB DIMM one rank 256MB DIMM one rank 256MB ECC-DIMM two ranks 512MB DIMM 256 Mbit (x 16) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) PC2100U-20330-C2 PC2100U-20330-A1 PC2100U-20220-A1 PC2100U-20330-A1 PC2100U-20330-B1 PC2100U-20220-B1 PC2100U-20330-B1 one rank 128MB DIMM one rank 256MB DIMM one rank 256MB ECC-DIMM one rank 256MB ECC-DIMM two ranks 512MB DIMM 256 Mbit (x 16) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) PC2700U-25330-C0 PC2700U-25330-A0 PC2700U-25330-A0 PC2700U-25330-B0 PC2700U-25330-B0 one rank 128MB DIMM one rank 256MB DIMM one rank 256MB ECC-DIMM two ranks 512MB DIMM 256 Mbit (x 16) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) PC3200U-30330-C0 PC3200U-30330-A0 PC3200U-30330-A0 PC3200U-30330-B0 PC3200U-30330-B0 one rank 128MB DIMM one rank 256MB DIMM one rank 256MB ECC-DIMM two ranks 512MB DIMM 256 Mbit (x 16) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) Ordering Information Compliance Code Description SDRAM Technology
two ranks 512MB ECC-DIMM 256 Mbit (x 8)
two ranks 512MB ECC-DIMM 256 Mbit (x 8)
two ranks 512MB ECC-DIMM 256 Mbit (x 8) two ranks 512MB ECC-DIMM 256 Mbit (x 8)
two ranks 512MB ECC-DIMM 256 Mbit (x 8)
Lead- and Halogene-Free DIMM Compliance Code Description SDRAM Technology
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D32000GU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "20330" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Pin Configuration
2
Table 4 Symbol A0 - A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7
Pin Configuration
Pin Definitions and Functions Type1) I I I/O I/O I I I/O I I I I/O I PWR GND PWR PWR AI PWR I I/O I NC Function Address Inputs Bank Selects Data Input/Output Check Bits (x 72 organization only) Command Inputs Clock Enable SDRAM low data strobes SDRAM clock (positive lines) SDRAM clock (negative lines) SDRAM low data mask/ high data strobes Chip Selects for Rank0 and Rank1 Power (+2.5 V) Ground I/O Driver power supply VDD Indentification flag I/O reference supply Serial EEPROM power supply Serial bus clock Serial bus data line slave address select Not Connected
RAS, CAS, WE CKE0 - CKE1 DQS0 - DQS8 CK0 - CK2, CK0 - CK2 DM0 - DM8 DQS9 - DQS17 S0, S1 VDD VSS VDDQ VDDID VREF VDDSPD SCL SDA SA0 - SA2 NC
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Pin Configuration Table 5 Frontside PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Symbol PIN# 48 49 50 51 52 Symbol A0 NC / CB2 Pin Configuration Backside PIN# 93 94 95 96 97 98 99 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ32 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 Symbol PIN# 140 141 142 143 144 Symbol NC / DM8/DQS17 A10 NC / CB6
VREF
DQ0
VSS
DQ4 DQ5
VSS
DQ1 DQS0 DQ2
VSS
NC / CB3 BA1 Key
VDDQD
DM0/DQS9 DQ6 DQ7
VDDQD
NC / CB7 Key
VDD
DQ3 NC NC
VSS
NC NC NC
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
VSS
DQ36 DQ37
VDDQ
DQ33 DQS4 DQ34
VSS
DQ8 DQ9 DQS1
VDD
DM4/DQS13 DQ38 DQ39
VDDQ
DQ12 DQ13 DM1/DQS10
VSS
BA0 DQ35 DQ40
VDDQ
CK1 CK1
VSS
DQ44 RAS DQ45
VDD
DQ14 DQ15 CKE1
VDDQ
WE DQ41 CAS
VSS
DQ10 DQ11 CKE0
VDDQ
S0 S1 DM5/DQS14
VDDQ
NC (BA2) DQ20 NC / A12
VSS
DQS5 DQ42 DQ43
VDDQ
DQ16 DQ17 DQS2
VSS
DQ46 DQ47 NC
VSS
DQ21 A11 DM2/DQS11
VDD
NC DQ48 DQ49
VSS
A9 DQ18 A7
VDDQ
DQ52 DQ53 NC (A13)
VDD
DQ22 A8 DQ23
VSS
CK2 CK2
VDDQ
DQ19 A5 DQ24
VDD
DM6/DQS15 DQ54 DQ55
VDDQ
DQS6 DQ50 DQ51
VSS
A6 DQ28 DQ29
VSS
DQ25 DQS3 A4
VDDQ
NC DQ60 DQ61
VSS VDDID
DQ56 DQ57
VDDQ
DM3/DQS12 A3 DQ30
VDD
DQ26
VSS
V1.1, 2003-07
Data Sheet
9
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Pin Configuration Table 5 Frontside PIN# 40 41 42 43 44 45 46 47 Symbol DQ27 A2 PIN# 85 86 87 88 89 90 91 92 Symbol Pin Configuration (cont'd) Backside PIN# 132 133 134 135 136 137 138 139 Symbol PIN# 177 178 179 180 181 182 183 184 Symbol DM7/DQS16 DQ62 DQ63
VDD
DQS7 DQ58 DQ59
VSS
DQ31 NC / CB4 NC / CB5
VSS
A1 NC / CB0 NC / CB1
VDDQ
SA0 SA1 SA2
VSS
NC SDA SCL
VDDQ
CK0 CK0
VDD
NC / DQS8
VSS
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC ("not connected") on x 64 organised non-ECC modules. Table 6 Density 128MB 256MB 256MB 512MB 512MB Address Format Organization 16M x 64 32M x 64 32M x 72 64M x 64 64M x 72 Memory Ranks 1 1 1 2 2 SDRAMs 16M x 16 32M x 8 32M x 8 32M x 8 32M x 8 # of SDRAMs 4 8 9 16 18 # of row/bank/ columns bits 13/2/10 13/2/11 13/2/11 13/2/11 13/2/11 Refresh 8K 8K 8K 8K 8K Period 64 ms 64 ms 64 ms 64 ms 64 ms Interval 7.8 s 7.8 s 7.8 s 7.8 s 7.8 s
Data Sheet
10
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Pin Configuration
S0 DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 S
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
S
D0
D2
DQS0 DM0/DQS9
DQS4 DM4/DQS13
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS2 DM2/DQS11
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
S
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
D1
DQS6 DM6/DQS15
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
S
D3
Serial PD SCL VDD SPD VDD /VDDQ VREF VSS VDDID SPD D0 - D3 D0 - D3 D0 - D3 Strap: see Note 4 WP A0 SA0 A1 SA1 A2 SA2 SDA
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 NC 2 SDRAMs 2 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D3 A0-A13: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 WE: SDRAMs D0 - D3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections (for memory device VDD, VDDQ ): STRAP OUT (OPEN): V DD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms 5%
Figure 1
Block Diagram - One Rank 16M x 64 DDR SDRAM DIMM HYS64D16301GU using x 16 organized SDRAMs
Data Sheet
11
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Pin Configuration
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS
DQS4 DM4/DQS13
S DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D4
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D6
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D7
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams BA0 - BA1 A0 - A13 RAS CAS CKE0 WE BA0-BA1: SDRAMs D0 - D7 A0-A13: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 VDD SPD VDD/VDDQ VREF VSS VDDID SPD D0 - D7 D0 - D7 D0 - D7 Strap: see Note 4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5% 4. VDDID strap connections (for memory device VDD , V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ . 5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms +5%
Figure 2
Block Diagram - One Rank 32M x 64 DDR-I SDRAM DIMM HYS64D32x00GU / HYS64D32300EU using x 8 organized SDRAMs
Data Sheet
12
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Pin Configuration
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D0
D8
D4
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D12
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D1
D9
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D13
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D10
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D14
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D11
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D15
VDD SPD VDD/VDDQ VREF VSS VDDID
SPD D0 - D15 D0 - D15 D0 - D15 Strap: see Note 4 SCL WP A0 SA0 SDA A1 SA1 A2 SA2 Serial PD
BA0 - BA1 A0 - A13 CKE1 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D15 A0-A13: SDRAMs D0 - D15 CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D15
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 4 SDRAMs 6 SDRAMs 6 SDRAMs
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5%
* Wire per Clock Loading Table/Wiring Diagrams
Figure 3
Block Diagram - Two Rank 64M x 64 DDR-I SDRAM DIMM HYS64D64x20GU using x 8 organized SDRAMs
Data Sheet
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Pin Configuration
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS
DQS4 DM4/DQS13
S DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D4
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D6
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D7
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
Serial PD SCL WP A0 SA0 SDA A1 SA1 A2 SA2
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 3 SDRAMs 3 SDRAMs 3 SDRAMs
D8
* Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D8 A0-A13: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 VDDSPD VDD/VDDQ VREF VSS VDDID
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be SPD maintained as shown. D0 - D8 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections D0 - D8 (for memory device VDD, V DDQ ): D0 - D8 STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ. Strap: see Note 4 5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm +5%
Figure 4
Block Diagram - One Rank 32M x 72 DDR-I SDRAM DIMM HYS72D32x00GU using x 8 organized SDRAMs
Data Sheet
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Pin Configuration
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D0
D9
D4
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D13
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D1
D10
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D14
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D11
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D15
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D12
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D16
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
VDD SPD VDD/VDDQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
SPD D0 - D17 D0 - D17 D0 - D17
VREF VSS VDDID Strap: see Note 4
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 6 SDRAMs 6 SDRAMs 6 SDRAMs
D8
D17
BA0 - BA1 A0 - A13 CKE1 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D17 A0-A13: SDRAMs D0 - D17 CKE: SDRAMs D9 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D17 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections SDA (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5%
* Wire per Clock Loading Table/Wiring Diagrams
Figure 5
Block Diagram - Two Rank 64M x 72 DDR-I SDRAM DIMM HYS72D64x20GU using x 8 organized SDRAMs
Data Sheet
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Pin Configuration
6 DRAM Loads
DRAM1
DRAM2 CK R = 120 5% DIMM Connector CK DRAM3 4 DRAM Loads
DRAM4 DRAM5
DRAM1
DRAM2 DRAM6 R = 120 5% DIMM Connector Cap.
Cap. 3 DRAM Loads DRAM1 DRAM5
Cap. R = 120 5% DIMM Connector DRAM3
DRAM6
Cap. 2 DRAM Loads DRAM5 DRAM1
Cap. DIMM Connector Cap.
Cap. R = 120 5% Cap.
1 DRAM Loads
Cap. DRAM5
Cap. R = 120 5% DIMM Connector DRAM3
Cap.
Cap. Cap.
Cap. Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF 20%
Figure 6
Clock Net Wiring
Data Sheet
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HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
3.1
Table 7 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -0.5 -0.5 -0.5 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on Inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature Power dissipation (per SDRAM component) Short Circuit Output Current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exceeding only one of these values for extended periods of time affect device reliability and may cause irreversible damage to the integrated circuit. Table 8 Parameter Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage Input Reference Voltage Input Reference Voltage Termination Voltage EEPROM supply voltage Supply Voltage Levels Symbol Limit Values min. nom. 2.5 2.6 2.5 2.6
VDDQ
Unit Note/ Test Condition max. 2.7 2.7 2.7 2.7 /2 V V V V V V V V
VDD VDD VDDQ VDDQ VREF VREF
VTT
2.3 2.5 2.3 2.5 0.49 x VDDQ
0.5 x VDDQ 0.51 x VDDQ
VDDQ / 2 -50
mV
VDDQ / 2 + 50
mV
fCK 166 MHz fCK > 166 MHz 1) fCK 166 MHz 2) fCK > 166 MHz 1)2) fCK 166 MHz 3) fCK > 166 MHz 1)3)
4)
VREF - 0.04
2.3
VREF
2.5
VREF + 0.04
3.6
VDDSPD
--
1) DDR400 conditions apply for all clock frequencies above 166 MHz 2) Under all conditions, VDDQ must be less than or equal to VDD. 3) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 4) VTT of the transmitting device must track VREF of the receiving device.
Data Sheet
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Electrical Characteristics
Table 9 Parameter
DC Operating Conditions (SSTL_2 Inputs) Symbol min. Values max. VDDQ + 0.3 VREF - 0.15 5 5 V V A A
2)
Unit
Note/ Test Condition 1)
DC Input Logic High DC Input Logic Low Input Leakage Current Output Leakage Current
VIH (DC) VIL (DC) IIL IOL
VREF + 0.15 - 0.30 -5 -5
-
3) 3)
1) VDDQ = 2.5 V, TA = 70 C, Voltage Referenced to VSS 2) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max.) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). 3) For any pin under test input of 0 V VIN VDDQ + 0.3 V. Values are shown per DDR SDRAM component
Data Sheet
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HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Table 10 Parameter
Current Conditions and Specification
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; tRC = tRC,MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; address and other control inputs stable at VIH,MIN or VIL,MAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, distributed refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
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Electrical Characteristics Table 11 Part Number & Organization Operating, Standby and Refresh Currents (PC2100, -8) HYS64D16301GU-8-B HYS64D32300GU-8-B HYS72D32300GU-8-B HYS64D64320GU-8-B HYS72D64320GU-8-B Unit Note1)2)
128MB x 64 1 rank typ. 288 332 20 120 72 52 168 356 384 504.8 6 632 max. 380 420 28 140 88 64 200 440 480 680 10 880
256MB x 64 1 rank typ. 560 640 40 240 144 104 320 632 680 1010 12 1200 max. 720 800 56 280 176 128 360 760 840 1360 20 1680
256MB x 72 1 rank typ. 630 720 45 270 162 117 360 711 765 1136 13.5 1350 max. 810 900 63 315 198 144 405 855 945 1530 22.5 1890
512MB x 64 2 ranks typ. 880 960 80 480 288 208 640 952 1000 1330 24 1520 max. 1080 1160 112 560 352 256 720 1120 1200 1720 40 2040
512MB x 72 2 ranks typ. 990 1080 90 540 324 234 720 1071 1125 1496 27 1710 max. 1215 1305 126 630 396 288 810 1260 1350 1935 45 2295 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
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Electrical Characteristics Table 12 HYS64D16301GU-7-B Operating, Standby and Refresh Currents (PC2100, -7 & -7F) HYS64D64320GU-7F-B HYS72D64320GU-7F-B HYS64D32300GU-7-B HYS64D32300EU-7-B HYS72D32300GU-7-B HYS64D64320GU-7-B HYS72D64320GU-7-B Unit Note
1)2)
Part Number & Organization
128MB x 64 1 rank
256MB x 64 1 rank
256MB x 72 1 rank
512MB x 64 1 rank
512MB x 72 1 rank
512MB x 72 2 ranks
512MB x 72 2 ranks max.
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
typ. max. typ. 308 420 376 460 22 80 60 32 100 72 140 160 600 720 44 280 160 120 400 760 840 12
max. typ. 800 880 64 320 200 144 440 920 675 810 315 180 135 450 855
max. typ. 900 990 360 225 162 495 747 882 315 180 135 450
max. typ. 990
max. typ.
max. typ.
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1000 1240 1125 1395 1197 1485 mA 88 560 320 240 800 128 640 400 288 880 99 630 360 270 900 144 720 450 324 990 99 630 360 270 900 144 720 450 324 990 mA mA mA mA mA
1080 1120 1320 1260 1485 1332 1575 mA 360 225 162 495
49.5 72
49.5 72
208 240 428 520 476 560 540 720 6 10 720 940
1035 855 1125 945
1035 1160 1360 1305 1530 1305 1530 mA 1125 1240 1440 1395 1620 1395 1620 mA 40 27 45 27 45 mA
1000 945 20
1080 1440 1215 1620 1217 1620 1480 1880 1665 2115 1667 2115 mA 13.5 22.5 13.5 22.5 24 1369 1800 1540 2025 1540 2025 1769 2240 1990 2520 1990 2520 mA
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
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Electrical Characteristics Table 13 Part Number & Organization Operating, Standby and Refresh Currents (PC2700, -6) HYS64D16301GU-6-B HYS64D32300GU-6-B HYS72D32300GU-6-B HYS64D64320GU-6-B HYS72D64320GU-6-B Unit Note
1)2)
128MB x 64 1 rank typ. 352 416 24 180 98.8 72 252 496 564 574 6 872 max. 460 500 36 220 112 84 280 640 660 760 10 1140
256MB x 64 1 rank typ. 680 800 48 360 197.6 144 480 880 1000 1148 12 1662 max. 880 960 72 440 224 168 520 1120 1160 1520 20 2160
256MB x 72 1 rank typ. 765 900 54 405 222.3 162 540 990 1125 1292 13.5 1870 max. 990 1080 81 495 252 189 585 1260 1305 1710 22.5 2430
512MB x 64 2 ranks typ. 1160 1280 96 720 395.2 288 960 1360 1480 1628 24 2142 max. 1400 1480 144 880 448 336 1040 1640 1680 2040 40 2680
512MB x 72 2 ranks typ. 1305 1440 108 810 444.6 324 1080 1530 1665 1832 27 2410 max. 1575 1665 162 990 504 378 1170 1845 1890 2295 45 3015 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
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Electrical Characteristics Table 14 Part Number & Organization Operating, Standby and Refresh Currents (PC3200, -5) HYS64D16301GU-5-B HYS64D32300GU-5-B HYS72D32300GU-5-B HYS64D64320GU-5-B HYS72D64320GU-5-B Unit Note1)2)
128MB x 64 1 rank typ. 400 460 24 184 96 68 240 560 600 620 6.4 1040 max. 480 540 36 224 136 96 296 700 720 780 10.4 1240
256MB x 64 1 rank typ. 720 840 48 368 192 136 456 920 1000 1240 12.8 1920 max. 920 1000 72 448 272 192 552 1160 1200 1560 20.8 2240
256MB x 72 1 rank typ. 810 945 54 414 216 153 513 1035 1125 1395 14.4 2160 max. 1035 1125 81 504 306 216 621 1305 1350 1755 23.4 2520
512MB x 64 2 ranks typ. 1176 1296 96 736 384 272 912 1376 1456 1696 25.6 2376 max. 1472 1552 144 896 544 384 1104 1712 1752 2112 41.6 2792
512MB x 72 2 ranks typ. 132 1458 108 828 432 306 1026 1548 1638 1908 28.8 2673 max. 1656 1746 162 1008 612 432 1242 1926 1971 2376 46.8 3141 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
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Electrical Characteristics
3.3
Table 15 Parameter
AC Characteristics
AC Timing - Absolute Specifications -8/-7/-7F Symbol Min. -8 DDR200 Max. +0.8 +0.8 0.55 0.55 12 12 12 12 -- -- -- -- +0.8 +0.8 1.25 +0.6 1.0 -- -- -- -- -- -- 0.60 -- Min. -0.75 -0.75 0.45 0.45 7 7 7.5 -- 0.5 0.5 2.2 1.75 -0.75 -0.75 0.75 -- -- -7 DDR266A Max. +0.75 +0.75 0.55 0.55 12 12 12 -- -- -- -- -- +0.75 +0.75 1.25 +0.5 0.75 -- -- -- -- -- -- 0.60 -- Min. -0.75 -0.75 0.45 0.45 7 7 7.5 -- 0.5 0.5 2.2 1.75 -0.75 -0.75 0.75 -- -- -7F DDR266 Max. +0.75 +0.75 0.55 0.55 12 12 12 -- -- -- -- -- +0.75 +0.75 1.25 +0.5 0.75 -- -- -- -- -- -- 0.60 -- ns ns
2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from tAC CK/CK DQS output access time from CK/CK CK high-level width
-0.8 -0.8 0.45 0.45 8 8 10 10 0.6 0.6 2.5 2.0 -0.8 -0.8 0.75 -- --
tDQSCK
2)3)4)5)
tCH CK low-level width tCL Clock Half Period tHP Clock cycle time tCK3 tCK2.5 tCK2 tCK1.5 DQ and DM input hold time tDH DQ and DM input setup tDS
time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK
tCK tCK
ns ns ns ns ns ns ns ns ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5)
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH) ns
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5)
tIPW tDIPW tHZ tLZ
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
Write command to 1st DQS tDQSS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time
tCK
ns ns ns
2)3)4)5)
tDQSQ tQHS tQH
2)3)4)5)
2)3)4)5) 2)3)4)5)
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
DQS input low (high) pulse tDQSL,H width (write cycle) DQS falling edge to CK setup time (write cycle)
tCK tCK tCK tCK
ns
2)3)4)5)
tDSS
2)3)4)5)
DQS falling edge hold time tDSH from CK (write cycle) Mode register set command tMRD cycle time Write preamble setup time Write postamble Write preamble
2)3)4)5)
2)3)4)5)
tWPRES tWPST tWPRE
2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
Data Sheet
24
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics Table 15 Parameter AC Timing - Absolute Specifications -8/-7/-7F (cont'd) Symbol Min. Address and control input setup time -8 DDR200 Max. -- -- -- -- 1.1 1.1 -- 0.60 120 E+3 -- -- -- -- -- -- -- Min. 0.9 1.0 0.9 1.0 0.9 NA NA 0.40 45 65 75 20 20 20 15 15 0.60 120 E+3 -- -- -- -- -- -- -- -7 DDR266A Max. -- -- -- -- 1.1 Min. 0.9 1.0 0.9 1.0 0.9 NA NA 0.40 45 60 75 15 15 15 15 15 0.60 120 E+3 -- -- -- -- -- -- -- -7F DDR266 Max. -- -- -- -- 1.1 ns ns ns ns fast slew rate
3)4)5)6)10)
Unit Note/ Test Condition 1)
tIS
1.1 1.1
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
1.1 1.1
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Read preamble Read preamble setup time Read postamble Active to Precharge command Active to Active/Autorefresh command period
tRPRE tRPRE1.5 tRPRES tRPST tRAS tRC
0.9 0.9 1.5 0.40 50 70 80 20 20 20 15 15
tCK tCK
ns
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)11)
2)3)4)5)12) 2)3)4)5) 2)3)4)5)
tCK
ns ns ns ns ns ns ns ns
2)3)4)5)
Auto-refresh to Active/Auto- tRFC refresh command period Active to Read or Write delay Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay command Exit self-refresh to read command Average Periodic Refresh Interval
2)3)4)5)
tRCD
2)3)4)5)
Precharge command period tRP
2)3)4)5) 2)3)4)5)
tRAP tRRD tWR tDAL
2)3)4)5)
2)3)4)5) 2)3)4)5)13)
(twr/tCK) + (trp/tCK) 1 2 80 200 -- -- -- -- -- 7.8 1 -- 75 200 -- -- -- -- -- 7.8 1 -- 75 200 -- -- -- -- -- 7.8
tCK tCK tCK
ns
tWTR tWTR1.5 Exit self-refresh to non-read tXSNR tXSRD tREFI
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5)
tCK
s
2)3)4)5)
2)3)4)5)14)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
25
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) CAS Latency 1.5 operation is supported on DDR200 devices only 12) tRPRES is defined for CL = 1.5 operation only 13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 16 Parameter
AC Timing - Absolute Specifications -6/-5 Symbol Min. -6 DDR333 Max. +0.7 +0.6 0.55 0.55 12 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.40 +0.45 +0.50 +0.55 -- -- Min. -0.6 -0.5 0.45 0.45 5 6 7.5 0.4 0.4 tbd tbd -0.6 -0.6 0.75 -- -- -- -- -5 DDR400B Max. +0.6 +0.5 0.55 0.55 12 12 12 -- -- -- -- +0.6 +0.6 1.25 +0.40 +0.40 +0.50 +0.50 -- -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.7 -0.6 0.45 0.45 6 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH) ns
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input)
tDH tDS tIPW
0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- -- -- --
tDIPW Data-out high-impedance time from CK/CK tHZ Data-out low-impedance time from CK/CK tLZ Write command to 1st DQS latching tDQSS
transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle)
2)3)4)5)6) 2)3)4)5)7) 2)3)4)5)7) 2)3)4)5)
tCK
ns ns ns ns ns
tDQSQ tQHS tQH tDQSL,H
TFBGA 2)3)4)5) TSOPII 2)3)4)5) TFBGA 2)3)4)5) TSOPII 2)3)4)5)
2)3)4)5)
tHP - tQHS
0.35
tHP - tQHS
0.35
tCK
2)3)4)5)
Data Sheet
26
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics Table 16 Parameter AC Timing - Absolute Specifications -6/-5 (cont'd) Symbol Min. DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time -6 DDR333 Max. -- -- -- -- 0.60 -- -- -- -- -- 1.1 0.60 -- -- -- -- -- -- -- Min. 0.2 0.2 2 0 0.40 0.25 0.6 NA 0.6 NA 0.9 0.40 55 65 15 15 15 10 15 1.1 0.60 -- -- -- -- -- -- -- -- -5 DDR400B Max. -- -- -- -- 0.60 -- -- Unit Note/ Test Condition 1)
2)3)4)5)
tDSS tDSH tMRD tWPRES tWPST tWPRE tIS
0.2 0.2 2 0 0.40 0.25 0.75 0.8
tCK tCK tCK
ns
2)3)4)5)
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
ns ns ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75 0.8
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay
tRPRE tRPST tRAS tRC tRFC
0.9 0.40 42 60 72 18 18 18 12 15
tCK tCK
ns ns ns ns ns ns ns
70E+3 40
70E+3 ns
2)3)4)5)
tRCD Precharge command period tRP Active to Autoprecharge delay tRAP Active bank A to Active bank B command tRRD Write recovery time tWR Auto precharge write recovery + precharge tDAL
time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11)
tCK
1 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tWTR tXSNR tXSRD tREFI
tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
27
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
28
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents
4
Table 17
SPD Contents
Operating, Standby and Refresh Currents (PC1600, -8) HYS64D16301GU-8-B HYS64D32300GU-8-B HYS72D32300GU-8-B HYS64D64320GU-8-B HYS72D64320GU-8-B 512MB x 72 2 ranks HEX 80 08 07 0D 0A 01 48 00 04 80 80 02 82 08 08 01 0E V1.1, 2003-07
Part Number & Organization
128MB x 64 1 rank HEX 80 08 07 0D 09 01 40 00 04 80 80
256MB x 64 1 rank HEX 80 08 07 0D 0A 01 40 00 04 80 80
256MB x 72 1 rank HEX 80 08 07 0D 0A 01 48 00 04 80 80
512MB x 64 2 ranks HEX 80 08 07 0D 0A 02 40 00 04 80 80
Byte 0 1 2 3 4 5 6 7 8 9 10
Description Number of SPD Bytes 128 Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels 256 DDR-SDRAM 13 9/10 1/2 x 64/x 72 0 SSTL_2.5
SDRAM Cycle Time at 8 ns CL = 2.5 Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Witdh 0.8 ns
11 12 13 14 15
non-ECC/ECC Self-Refresh 7.8 s x 16/ x 8 na/ x 8
00 82 10 00 01
00 82 08 00 01
02 82 08 08 01
00 82 08 00 01
Minimum Clock Delay tCCD = 1 CLK for Back-to-Back Random Column Address Burst Length Supported 2, 4 & 8
16
0E
0E
0E
0E
Data Sheet
29
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 17 Operating, Standby and Refresh Currents (PC1600, -8) (cont'd) HYS64D16301GU-8-B HYS64D32300GU-8-B HYS72D32300GU-8-B HYS64D64320GU-8-B Part Number & Organization HYS72D64320GU-8-B 512MB x 72 2 ranks HEX 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 40 B0 B0 V1.1, 2003-07
128MB x 64 1 rank HEX 04
256MB x 64 1 rank HEX 04 0C 01 02 20 C0 A0 80
256MB x 72 1 rank HEX 04 0C 01 02 20 C0 A0 80
512MB x 64 2 ranks HEX 04 0C 01 02 20 C0 A0 80
Byte 17 18 19 20 21 22 23 24
Description Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General 4
CAS latency = 2 & 2.5 0C CS latency = 0 Write latency = 1 unbuffered - 01 02 20 C0 A0 80
Min. Clock Cycle Time 10 ns at CAS Latency = 2 Access Time from Clock for CL = 2 0.8 ns
25 26
Minimum Clock Cycle not supported Time for CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time not supported
00 00
00 00
00 00
00 00
27 28 29 30 31 32 33
20 ns
50 3C 50 32 20 B0 B0
50 3C 50 32 40 B0 B0
50 3C 50 32 40 B0 B0
50 3C 50 32 40 B0 B0
Minimum Row Act. to 15 ns Row Act. Delay tRRD Minimum RAS to CAS 20 ns Delay tRCD Minimum RAS Pulse Width tRAS 50 ns
Module Bank Density 256 MByte (per Bank) Addr. and Command Setup Time 1.1 ns
Addr. and Command 1.1 ns Hold Time
Data Sheet
30
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 17 Operating, Standby and Refresh Currents (PC1600, -8) (cont'd) HYS64D16301GU-8-B HYS64D32300GU-8-B HYS72D32300GU-8-B HYS64D64320GU-8-B Part Number & Organization HYS72D64320GU-8-B 512MB x 72 2 ranks HEX 60 60 00 46 50 30 3C A0 00 00 B9 C1 Infineon - - - - - - - V1.1, 2003-07
128MB x 64 1 rank HEX 60 60 00 46 50 30 3C A0 00 00 E8 C1 Infineon - - - - - - -
256MB x 64 1 rank HEX 60 60 00 46 50 30 3C A0 00 00 A7 C1 Infineon - - - - - - -
256MB x 72 1 rank HEX 60 60 00 46 50 30 3C A0 00 00 B9 C1 Infineon - - - - - - -
512MB x 64 2 ranks HEX 60 60 00 46 48 30 3C A0 00 00 A8 C1 Infineon - - - - - - -
Byte 34 35 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127
Description Data Input Setup Time 0.6 ns Data Input Hold Time 0.6 ns Superset Information - Minimum Core Cycle 70 ns Time tRC Min. Auto Refresh 80 ns Cmd Cycle Time tFRC Maximum Clock Cycle 12 ns Time tCK Max. DQS-DQ Skew 0.6 ns
tDQSQ
X-Factor tQHS Superset Information SPD Revision 1.0 ns - Revision 0.0
Checksum for Bytes 0 - - 62 Manufacturers JEDEC ID Codes Manufacturer Module Location Module Code - -
Assembly - -
Module Part Number
Revision - -
Module Manufacturing Date - for
Module Serial Number - - Customer -
128 to 255 open use
Data Sheet
31
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 18 SPD Codes for PC2100 Modules "-7" HYS64D16301GU-7-B HYS64D32300GU-7-B HYS64D32300EU-7-B HYS72D32300GU-7-B HYS64D64320GU-7-B Part Number & Organization HYS72D64320GU-7-B 512MB x 72 2 ranks HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01 0E 04 V1.1, 2003-07
128MB x 64 1 rank HEX 80 08 07 0D 09 01 40 00 04 70 75
256MB x 64 1 rank HEX 80 08 07 0D 0A 01 40 00 04 70 75
256MB x 72 1 rank HEX 80 08 07 0D 0A 01 48 00 04 70 75
512MB x 64 2 ranks HEX 80 08 07 0D 0A 02 40 00 04 70 75
Byte 0 1 2 3 4 5 6 7 8 9 10
Description Number of SPD Bytes 128 Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels 256 DDR-SDRAM 13 9/10 1/2 x 64/x 72 0 SSTL_2.5
SDRAM Cycle Time at 7 ns CL = 2.5 Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Witdh 0.75 ns
11 12 13 14 15
non-ECC/ECC Self-Refresh 7.8 s x 16/ x 8 na/ x 8
00 82 10 00 01
00 82 08 00 01
02 82 08 08 01
00 82 08 00 01
Minimum Clock Delay tCCD = 1 CLK for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks 2, 4 & 8 4
16 17
0E 04
0E 04
0E 04
0E 04
Data Sheet
32
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 18 SPD Codes for PC2100 Modules "-7" (cont'd) HYS64D16301GU-7-B HYS64D32300GU-7-B HYS64D32300EU-7-B HYS72D32300GU-7-B HYS64D64320GU-7-B Part Number & Organization HYS72D64320GU-7-B 512MB x 72 2 ranks HEX 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 40 90 90 50 50 V1.1, 2003-07
128MB x 64 1 rank HEX
256MB x 64 1 rank HEX 0C 01 02 20 C0 75 75
256MB x 72 1 rank HEX 0C 01 02 20 C0 75 75
512MB x 64 2 ranks HEX 0C 01 02 20 C0 75 75
Byte 18 19 20 21 22 23 24
Description Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General
CAS latency = 2 & 2.5 0C CS latency = 0 Write latency = 1 unbuffered - 01 02 20 C0 75 75
Min. Clock Cycle Time 7.5 ns at CAS Latency = 2 Access Time from Clock for CL = 2 0.75 ns
25 26
Minimum Clock Cycle not supported Time for CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD not supported
00 00
00 00
00 00
00 00
27 28 29 30 31 32 33 34 35
20 ns 15 ns
50 3C 50 2D
50 3C 50 2D 40 90 90 50 50
50 3C 50 2D 40 90 90 50 50
50 3C 50 2D 40 90 90 50 50
Minimum RAS to CAS 20 ns Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per Bank) Addr. and Command Setup Time 45 ns
128 MByte/256 MByte 20 0.9 ns 90 90 50 50
Addr. and Command 0.9 ns Hold Time Data Input Setup Time 0.5 ns Data Input Hold Time 0.5 ns
Data Sheet
33
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 18 SPD Codes for PC2100 Modules "-7" (cont'd) HYS64D16301GU-7-B HYS64D32300GU-7-B HYS64D32300EU-7-B HYS72D32300GU-7-B HYS64D64320GU-7-B Part Number & Organization HYS72D64320GU-7-B 512MB x 72 2 ranks HEX 00 41 4B 30 32 75 00 00 C4 C1 Infineon - - - - - - - V1.1, 2003-07
128MB x 64 1 rank HEX 00 41 4B 30 32 75 00 00 99 C1 Infineon - - - - - - -
256MB x 64 1 rank HEX 00 41 4B 30 32 75 00 00 B2 C1 Infineon - - - - - - -
256MB x 72 1 rank HEX 00 41 4B 30 32 75 00 00 C4 C1 Infineon - - - - - - -
512MB x 64 2 ranks HEX 00 41 4B 30 32 75 00 00 B3 C1 Infineon - - - - - - -
Byte 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127
Description Superset Information - Minimum Core Cycle 65 ns Time tRC Min. Auto Refresh 75 ns Cmd Cycle Time tFRC Maximum Clock Cycle 12 ns Time tCK Max. DQS-DQ Skew 0.5 ns
tDQSQ
X-Factor tQHS Superset Information SPD Revision 0.75 ns - Revision 0.0
Checksum for Bytes 0 - - 62 Manufacturers JEDEC ID Codes Manufacturer Module Location Module Code - -
Assembly - -
Module Part Number
Revision -
Module Manufacturing - Date Module Serial Number - - for - Customer -
128 to 255 open use
Data Sheet
34
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 19 SPD Codes for PC2100 Modules "-7F" HYS72D32300GU-7F-B HYS64D64320GU-7F-B 512MB x 72 1 rank HEX 80 08 07 0D 0A 02 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 20 C0 V1.1, 2003-07
Part Number & Organization
256MB x 72 1 rank HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Description Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary 128 256 DDR-SDRAM 13 9/10 1/2 x 64/x 72 0 SSTL_2.5 7 ns 0.75 ns non-ECC/ECC Self-Refresh 7.8 s x 16/ x 8
Error Checking SDRAM Data na/ x 8 Witdh Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General
tCCD = 1 CLK
16 17 18 19 20 21 22
2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered -
0E 04 0C 01 02 20 C0
Data Sheet
35
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 19 SPD Codes for PC2100 Modules "-7F" (cont'd) HYS72D32300GU-7F-B HYS64D64320GU-7F-B 512MB x 72 1 rank HEX 75 75 00 00 3C 3C 3C 2D 40 90 90 50 50 00 3C 4B 30 32 75 V1.1, 2003-07
Part Number & Organization
256MB x 72 1 rank HEX 75 75 00 00 3C 3C 3C 2D 40 90 90 50 50 00 3C 4B 30 32 75
Byte 23 24 25 26 27 28 29 30 31 32 33 34 35 36 to 40 41 42 43 44 45
Description Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time for CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD 7.5 ns 0.75 ns not supported not supported 15 ns 15 ns
Minimum RAS to CAS Delay 15 ns
tRCD
Minimum RAS Pulse Width 45 ns 128 MByte/256 MByte 0.9 ns
tRAS
Module Bank Density (per Bank) Addr. and Command Setup Time
Addr. and Command Hold 0.9 ns Time Data Input Setup Time Data Input Hold Time Superset Information 0.5 ns 0.5 ns -
Minimum Core Cycle Time 60 ns
tRC
Min. Auto Refresh Cmd Cycle 75 ns Time tFRC Maximum Clock Cycle Time 12 ns
tCK
Max. DQS-DQ Skew tDQSQ X-Factor tQHS 0.5 ns 0.75 ns
Data Sheet
36
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 19 SPD Codes for PC2100 Modules "-7F" (cont'd) HYS72D32300GU-7F-B HYS64D64320GU-7F-B 512MB x 72 1 rank HEX 00 00 98 C1 Infineon - - - - - - - V1.1, 2003-07
Part Number & Organization
256MB x 72 1 rank HEX 00 00 97 C1 Infineon - - - - - - -
Byte 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127
Description Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufactures Codes Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number - JEDEC - Revision 0.0 - ID - - - - - - - - -
128 to 255 open for Customer use
Data Sheet
37
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 20 SPD Codes for PC2700 Modules "-6" HYS64D16301GU-6-B HYS64D32300GU-6-B HYS72D32300GU-6-B HYS64D64320GU-6-B Part Number & Organization HYS72D64320GU-6-B 512MB x 72 2 ranks HEX 80 08 07 0D 0A 01 48 00 04 60 70 02 82 08 08 01 0E 04 V1.1, 2003-07
128MB x 64 1 rank HEX 80 08 07 0D 09 01 40 00 04 60 70
256MB x 64 1 rank HEX 80 08 07 0D 0A 01 40 00 04 60 70
256MB x 72 1 rank HEX 80 08 07 0D 0A 01 48 00 04 60 70
512MB x 64 2 ranks HEX 80 08 07 0D 0A 02 40 00 04 60 70
Byte 0 1 2 3 4 5 6 7 8 9 10
Description Number of SPD Bytes 128 Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels 256 DDR-SDRAM 13 9/10 1/2 x 64/x 72 0 SSTL_2.5
SDRAM Cycle Time at 6 ns CL = 2.5 Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Witdh 0.75 ns
11 12 13 14 15
non-ECC/ECC Self-Refresh 7.8 s x 16/ x 8 na/ x 8
00 82 10 00 01
00 82 08 00 01
02 82 08 08 01
00 82 08 00 01
Minimum Clock Delay tCCD = 1 CLK for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks 2, 4 & 8 4
16 17
0E 04
0E 04
0E 04
0E 04
Data Sheet
38
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 20 SPD Codes for PC2700 Modules "-6" (cont'd) HYS64D16301GU-6-B HYS64D32300GU-6-B HYS72D32300GU-6-B HYS64D64320GU-6-B Part Number & Organization HYS72D64320GU-6-B 512MB x 72 2 ranks HEX 0C 01 02 20 C0 75 70 00 00 48 30 48 2A 40 75 75 45 45 V1.1, 2003-07
128MB x 64 1 rank HEX
256MB x 64 1 rank HEX 0C 01 02 20 C0 75 70
256MB x 72 1 rank HEX 0C 01 02 20 C0 75 70
512MB x 64 2 ranks HEX 0C 01 02 20 C0 75 70
Byte 18 19 20 21 22 23 24
Description Supported CAS Latencies CS Latencies WE Latencies
CAS latency = 2 & 2.5 0C CS latency = 0 Write latency = 1 01 02 20 C0 75 70
SDRAM DIMM Module unbuffered Attributes SDRAM Device Attributes: General -
Min. Clock Cycle Time 7.5 ns at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time for CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD 0.70 ns
25 26
not supported not supported
00 00
00 00
00 00
00 00
27 28 29 30 31 32 33 34 35
18 ns 12 ns
48 30 48 2A
48 30 48 2A 40 75 75 45 45
48 30 48 2A 40 75 75 45 45
48 30 48 2A 40 75 75 45 45
Minimum RAS to CAS 18 ns Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per Bank) Addr. and Command Setup Time 42 ns
128 MByte/256 MByte 20 0.75 ns 75 75 45 45
Addr. and Command 0.75 ns Hold Time Data Input Setup Time 0.45 ns Data Input Hold Time 0.45 ns
Data Sheet
39
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 20 SPD Codes for PC2700 Modules "-6" (cont'd) HYS64D16301GU-6-B HYS64D32300GU-6-B HYS72D32300GU-6-B HYS64D64320GU-6-B Part Number & Organization HYS72D64320GU-6-B 512MB x 72 2 ranks HEX 00 3C 48 30 2D 55 00 00 12 C1 Infineon - - - - - - - V1.1, 2003-07
128MB x 64 1 rank HEX 00 3C 48 30 2D 55 00 00 E7 C1 Infineon - - - - - - -
256MB x 64 1 rank HEX 00 3C 48 30 2D 55 00 00 00 C1 Infineon - - - - - - -
256MB x 72 1 rank HEX 00 3C 48 30 2D 55 00 00 12 C1 Infineon - - - - - - -
512MB x 64 2 ranks HEX 00 3C 48 30 2D 55 00 00 01 C1 Infineon - - - - - - -
Byte 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127
Description Superset Information - Minimum Core Cycle 60 ns Time tRC Min. Auto Refresh 72 ns Cmd Cycle Time tFRC Maximum Clock Cycle 12 ns Time tCK Max. DQS-DQ Skew 0.45 ns
tDQSQ
X-Factor tQHS Superset Information SPD Revision 0.55 ns - Revision 0.0
Checksum for Bytes 0 - - 62 Manufacturers JEDEC - ID Codes Manufacturer Module Location - Assembly - -
Module Part Number
Module Revision Code - Module Manufacturing - Date Module Serial Number - - -
128 to 255 open for Customer use -
Data Sheet
40
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 21 SPD Codes for PC3200 Modules "-5" HYS64D16301GU-5-B HYS64D32300GU-5-B HYS72D32300GU-5-B HYS64D64320GU-5-B Part Number & Organization HYS72D64320GU-5-B x 72 HEX 80 08 07 0D 0A 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 V1.1, 2003-07
128MB 256MB 256MB 512MB 512MB x 64 HEX x 64 HEX 80 08 07 0D 0A 01 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 x 72 HEX 80 08 07 0D 0A 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 x 64 HEX 80 08 07 0D 0A 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C 28 1 rank 1 rank 1 rank 2 ranks 2 ranks 80 08 07 0D 09 01 40 00 04 50 50 00 82 10 00 01 0E 04
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type DDR-I = 07h # of Row Addresses # Number of Column Addresses # of DIMM Banks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Refresh Rate Primary SDRAM width Error Checking SDRAM width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM CAS Latency CS Latency WE (Write) Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin (ns) tRRDmin [ns] 128 256 DDR-SDRAM 13 9/10 1/2 x 64/x 72 0 SSTL_2.5 5 ns 0.50 ns Self-Refresh 7.8 s x 16/ x 8 na/ x 8
DIMM Configuration Type (non- / ECC) non-ECC/ECC
tCCD = 1 CLK
2, 4 & 8 4
CAS latency = 2, 1C 2.5, 3 CS latency = 0 unbuffered - 6.0 ns 0.50 ns 7.5 ns not supported 15 ns 10 ns 01 20 C1 60 50 75 50 3C 28 Write latency = 1 02
Data Sheet
41
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 21 SPD Codes for PC3200 Modules "-5" (cont'd) HYS64D16301GU-5-B HYS64D32300GU-5-B HYS72D32300GU-5-B HYS64D64320GU-5-B Part Number & Organization HYS72D64320GU-5-B x 72 HEX 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 10 C1 49 4E 46 49 4E 45 4F xx 37 32 44 V1.1, 2003-07
128MB 256MB 256MB 512MB 512MB x 64 HEX x 64 HEX 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 FD C1 49 4E 46 49 4E 45 4F xx 36 34 44 x 72 HEX 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 0F C1 49 4E 46 49 4E 45 4F xx 37 32 44 x 64 HEX 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 FE C1 49 4E 46 49 4E 45 4F xx 36 34 44 1 rank 1 rank 1 rank 2 ranks 2 ranks 3C 28 20 60 60 40 40 00 37 41 28 28 50 00 00 E4 C1 49 4E 46 49 4E 45 4F xx 36 34 44
Byte 29 30 31 32 33 34 35 36 40 41 42 43 44 45 46 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Description tRCDmin [ns] tRASmin [ns] Module Density per Bank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used SPD Revision Checksum of Byte 0-62 (LSB only) JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon Module Manufacturer Location Module Part Number, Char 1 Module Part Number, Char 2 Module Part Number, Char 3 15 ns 40 ns 128 MByte/ 256 MByte 0.60 ns 0.60 ns 0.40 ns 0.40 ns - 55 ns 65 ns 10 ns 0.40 ns 0.50 ns - Revision 0.0 - - "I" "N" "F" "I" "N" "E" "O" - - - -
Data Sheet
42
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 21 SPD Codes for PC3200 Modules "-5" (cont'd) HYS64D16301GU-5-B HYS64D32300GU-5-B HYS72D32300GU-5-B HYS64D64320GU-5-B Part Number & Organization HYS72D64320GU-5-B x 72 HEX 36 34 33 32 30 47 55 35 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00 V1.1, 2003-07
128MB 256MB 256MB 512MB 512MB x 64 HEX x 64 HEX 33 32 33 30 30 47 55 35 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00 x 72 HEX 33 32 33 30 30 47 55 35 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00 x 64 HEX 36 34 33 32 30 47 55 35 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00 1 rank 1 rank 1 rank 2 ranks 2 ranks 31 36 33 30 31 47 55 35 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00
Byte 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 127
Description Module Part Number, Char 4 Module Part Number, Char 5 Module Part Number, Char 6 Module Part Number, Char 7 Module Part Number, Char 8 Module Part Number, Char 9 Module Part Number, Char 10 Module Part Number, Char 11 Module Part Number, Char 12 Module Part Number, Char 13 Module Part Number, Char 14 Module Part Number, Char 15 Module Part Number, Char 16 Module Part Number, Char 17 Module Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Module Serial Number Module Serial Number Module Serial Number not used - - - - - - - - - - - - - - - - - - - - - - - -
Data Sheet
43
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
5
0.1 A B C
Package Outlines
133.35 128.95 2.7 MAX. A
1)
0.15 A B C
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-18
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 7 Package Outline - Raw Card C (128 MByte, 1 Rank Module)
Data Sheet
44
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-29
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 8 Package Outline - Raw Card A (256 MByte, 1 Rank Module, -7 and -8)
Data Sheet
45
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-9
3 MIN.
Detail of contacts
1)
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 9 Package Outline - Raw Card B (512 MByte, 2 Rank Module, -7 and -8)
Data Sheet
46
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-30
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 10 Package Outline - Raw Card A (256 MByte, 1 Rank Module, -5 and -6, ECC)
Data Sheet
47
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-31
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 11 Package Outline - Raw Card B (512 MByte, 2 Rank Module, -5 and -6, ECC)
Data Sheet
48
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-32
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 12 Package Outline - Raw Card A (256 MByte, 1 Rank Module, -5 and -6, Non ECC)
Data Sheet
49
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-33
Figure 13
Package Outline - Raw Card B (512 MByte, 2 Rank Module, -5 and -6, Non ECC)
Data Sheet
50
V1.1, 2003-07
17.8
www.infineon.com
Published by Infineon Technologies AG

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